For PLL circuits, in general, a difference in phase between reference signals and output signals of VCO (voltage controlled oscillator) is detected, and a control voltage corresponding to the phase difference is produced and fed to VCO, thereby controlling the frequency. Further, a loop filter is provided to remove a high-frequency component contained in the control voltage, thereby permitting the circuit to be operated stably against noises.
In the above PLL circuits, increasing the time constant of the loop filter can reduce the high-frequency component contained in the control voltage in the VCO, resulting in enhanced noise resistance of the PLL loop. This, however, prolongs the lead-in (pull-in) time of the PLL loop, deteriorating the quick response. Therefore, devices using the above PLL circuit have the problem that, when the frequency is changed, the lead-in time exceeds the time limit, inhibiting normal operation.
On the other hand, one type of a conventional PLL circuit disclosed in the Japanese Patent Kokai No. 61-81027. This conventional PLL circuit comprises a VCO having two input terminals, to the first one of which a loop filter is connected, and to the second one of which a bias voltage control circuit is connected.
In operation, when a channel is newly set, the bias voltage control circuit generates a bias voltage corresponding to the newly set channel, and the generated bias voltage is applied to the second input terminal of the VCO, so that an output frequency of the VCO is instantly shifted to a predetermined frequency in response to the setting of the new channel.
In the conventional PLL circuit, however, there are disadvantages in that the VCO is required to have the two input terminals, and the VCO must be switched over between the two input terminals. As a result, the cost of the PLL circuit must be increased, and the structure of the VCO becomes complicated, because practically used VCOs can not be applicable thereto.